1. Field of the Invention
The present invention pertains to the field of integrated circuits. More particularly, this invention relates to a decoder circuit having short channel depletion transistors that yield low resistance signal paths.
2. Description of the Related Art
Integrated circuit devices such as programmable logic devices or non-volatile memory devices typically include a variety of decoder circuits. Such decoder circuits are commonly implemented as arrays of transistors. Such an array usually includes multiple columns of series coupled transistors. Typically, multiple rows of polysilicon lines provide connections to the gates of the transistor columns.
The decoding function for such a decoder circuit is commonly preset during integrated circuit device manufacturing steps. Such steps usually include the formation of a low resistance or short circuit signal paths between the source and drain regions of selected transistors in the decoder circuit.
One prior technique for forming a low resistance signal path between the source and drain regions of a transistor in such a decoder circuit involves the formation of a programming junction within the channel region of the transistor. Typically, such a programming junction is formed with a high energy high dose n+ implant into the channel region of the transistor before the formation of the polysilicon gate structure of the transistor. Such an n+ implant usually yields a low resistance path and effectively creates a short circuit between source and drain in the transistor.
Unfortunately, such a high energy implant for the programming junction usually damages the surface of the silicon wafer and creates various types of surface imperfections on the silicon wafer. Such imperfections typically reduce the quality of a gate oxide layer subsequently formed on the damaged surface over the programming junction. Such a poor quality gate oxide is commonly subject to breakdown and which may cause short circuiting between the polysilicon gate and the channel region of the transistor and consequential failure of the decoder circuit.
Such gate oxide breakdown is an even greater problem in decoder circuits that operate at voltages higher than the VCC supply voltage to the integrated circuit device. Such decoder circuitry that operates at high voltages is common in programmable logic devices and non-volatile memories that employ high voltages in high speed logic.
Another prior technique for forming a low resistance signal path between the source and drain regions of a transistor in such a decoder circuit involves the formation of a salicidation local interconnect structure above the polysilicon gate. Such a local interconnect typically involves the reaction of a titanium layer and an amorphous silicon layer onto an oxide layer that protects the polysilicon gate. Unfortunately, such salicidation structures are typically difficult to scale down to smaller and smaller dimensions on the silicon wafer substrate due to the reflections caused by the amorphous silicon and titanium layers during the photolithography steps.
Yet another prior art method for forming a low resistance signal path between the source and drain regions of a transistor involves using a Metal I layer over the surface of the silicon gate layer and forming contacts on the surface of the source and drain regions. Such an "overpass" structure is difficult to scale down to small dimensions.